library ieee;
use ieee.std_logic_1164.all;
use work.cpu_utils.all;
use work.alu_utils.all;


entity test_reg_file is
	
end entity test_reg_file;

architecture RTL of test_reg_file is
	
	component alu
		generic (
			size: integer := 32;
			Tpd : Time := unit_delay
		);
		port (
			operand1 : in bit_vector(size-1 downto 0);
			operand2 : in bit_vector(size-1 downto 0);
			result : out bit_vector(size-1 downto 0);
			condition_flag : out bit_vector(2 downto 0);--n z v : 2 1 0
			command : in ALU_command
		);
	end component;
	
	component controlUnit
		generic(
			register_size : integer := 32;
			Tpd : Time := unit_delay
		);
		port(
			reset_in: in bit;
			CC, V, SPV : in bit;
			opcode: in bit_vector (5 downto 0);--IR 5 downto 0
			Z: in bit_vector (register_size-1 downto 0);
			
			read: out bit;
			write: out bit;
			st_cond: out bit;
			
			ldIR: out bit;
			ldA: out bit;
			ldB: out bit;
			ldZ: out bit;
			ldMAR: out bit;
			ldMDR: out bit;
			
			mar_mux_s0: out bit;
			a_mux_s0: out bit;
			gpr_src_mux_s0: out bit;
			b_mux_s0: out bit;
			imm_mux_s0: out bit;
			imm_mux_s1: out bit;
			pc_gpr_mux_s0: out bit;
			mdr_mux_s0: out bit;
			mdr_mux_s1: out bit;
			
			alu_cmd: out ALU_command;
			
			Gpr_H_in: out bit;
			Gpr_L_in: out bit;
			ldIMM: out bit;
			
			push: out bit;
			pop: out bit;
			clSP: out bit;
			decSP: out bit;
			incSP: out bit;
			
			clPC: out bit;
			ldPC: out bit;
			
			clock: in bit
		);
	end component;
	
	signal op1, op2, Z : bit_vector(31 downto 0);
	signal cond_flag: bit_vector(2 downto 0);
	signal ALU_op: ALU_command;
	signal clk, reset, cond, sp_v, rd, wr, stCnd,ldIR1,
			ldA1, ldB2,
			ldz1, ldmar1,
			ldmdr1, marmuxso, amuxso, gprmuxs0,
			 b_muxs0,  imm0,
			imm1, pcmux0, mdrmuxs0, mdrmuxs1,
			 Hin, Lin, immld,
			 push1, pop1, spcl, spdec, spinc,
			 pccl, pcld: bit;
	signal IR : bit_vector(5 downto 0);
begin
	ALU_imp: alu
		port map(
					operand1 => op1, operand2 => op2, result => Z, 
					condition_flag => cond_flag, command => ALU_op
				);
				
	ctrl_unit: controlUnit
		port map(
			reset_in=>reset,
			CC=>cond, V=>cond_flag(0), SPV=>sp_v,
			opcode=>IR,
			Z=>Z,
			
			read=>rd,
			write=>wr,
			st_cond=>stCnd,
			
			ldIR=>ldIR1,
			ldA=>ldA1,
			ldB=>ldB2,
			ldZ=>ldz1,
			ldMAR=>ldmar1,
			ldMDR=>ldmdr1,
			
			mar_mux_s0=>marmuxso,
			a_mux_s0=>amuxso,
			gpr_src_mux_s0=>gprmuxs0,
			b_mux_s0=>b_muxs0,
			imm_mux_s0=>imm0,
			imm_mux_s1=>imm1,
			pc_gpr_mux_s0=>pcmux0,
			mdr_mux_s0=>mdrmuxs0,
			mdr_mux_s1=>mdrmuxs1,
			
			alu_cmd=>ALU_op,
			
			Gpr_H_in=>Hin,
			Gpr_L_in=>Lin,
			ldIMM=>immld,
			
			push=>push1,
			pop=>pop1,
			clSP=>spcl,
			decSP=>spdec,
			incSP=>spinc,
			
			clPC=>pccl,
			ldPC=>pcld,
			
			clock=>clk
		);
end architecture RTL;
